1 data sheet acquired from harris semiconductor schs210f features buffered inputs typical propagation delay: 8ns at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c4075 and ?ct4075 logic gates utilize silicon-gate cmos technology to achieve operating speeds similar to lsttl gates with the low power consumption of standard cmos integrated circuits. all devices have the ability to drive 10 lsttl loads. the hct logic family is functionally pin compatible with the standard ls logic family. pinout cd54hc4075, cd54hct4075 (cerdip) cd74hc4075 (pdip, soic, sop, tssop) cd74hct4075 (pdip) top view ordering information part number temp. range ( o c) package CD54HC4075F3A -55 to 125 14 ld cerdip cd54hct4075f3a -55 to 125 14 ld cerdip cd74hc4075e -55 to 125 14 ld pdip cd74hc4075m -55 to 125 14 ld soic cd74hc4075mt -55 to 125 14 ld soic cd74hc4075m96 -55 to 125 14 ld soic cd74hc4075nsr -55 to 125 14 ld sop cd74hc4075pw -55 to 125 14 ld tssop cd74hc4075pwr -55 to 125 14 ld tssop cd74hc4075pwt -55 to 125 14 ld tssop cd74hct4075e -55 to 125 14 ld pdip note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. 2a 2b 1a 1b 1c 1y gnd v cc 3c 3b 3a 3y 2y 2c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 august 1997 - revised august 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc4075, cd74hc4075, cd54hct4075, cd74hct4075 high-speed cmos logic triple 3-input or gate [ /title ( cd74h c 4075, c d74h c t4075) / subject ( high s peed c mos l ogic t riple 3- i nput
2 functional diagram logic diagram truth table inputs output na nb nc ny llll hxxh xhxh xxhh h = high voltage level, l = low voltage level, x = irrelevant 1a 1c 2b 2c 3b 3 5 1 2 11 12 6 2y 2a gnd = 7 v cc = 14 3a 1b 4 8 13 3c 1y 3y 9 10 na nb ny nc cd54hc4075, cd74hc4075, cd54hct4075, cd74hct4075
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) package thermal impedance, ja (see note 1): e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 o c/w m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 o c/w ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 o c/w pw (tssop) package . . . . . . . . . . . . . . . . . . . . . . . . . 113 o c/w maximum junction temperature (hermetic package or die) . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 2 - 20 - 40 a cd54hc4075, cd74hc4075, cd54hct4075, cd74hct4075
4 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 2 - 20 - 40 a additional quiescent device current per input pin: 1 unit load ? i cc (note 2) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 2. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 1.6 note: unit load is ? i cc limit speci?d in dc electrical table, e.g. 360 a max at 25 o c. switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, input to output (figure 1) t plh, t phl c l = 50pf 2 - - 100 - 125 - 150 ns 4.5 - - 20 - 25 - 30 ns 6 - - 17 - 21 - 26 ns c l = 15pf 5 - 8 - - - - - ns transition times (figure 1) t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c in - - - - 10 - 10 - 10 pf cd54hc4075, cd74hc4075, cd54hct4075, cd74hct4075
5 power dissipation capacitance (notes 3, 4) c pd -5-26-----pf hct types propagation delay, input to output (figure 2) t plh , t phl c l = 50pf 4.5 - - 24 - 30 - 36 ns c l = 15pf 5 - 9 - - - - - ns transition times (figure 2) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c in - - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd -5-28-----pf notes: 3. c pd is used to determine the dynamic power consumption, per gate. 4. p d = v cc 2 f i (c pd + c l ) where f i = input frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms figure 1. hc and hcu transition times and propaga- tion delay times, combination logic figure 2. hct transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54hc4075, cd74hc4075, cd54hct4075, cd74hct4075
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-8772201ca active cdip j 14 1 tbd call ti level-nc-nc-nc CD54HC4075F3A active cdip j 14 1 tbd call ti level-nc-nc-nc cd54hct4075f3a active cdip j 14 1 tbd call ti level-nc-nc-nc cd74hc4075e active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc4075m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075nsr active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075nsrg4 active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pw active tssop pw 14 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pwe4 active tssop pw 14 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pwr active tssop pw 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pwre4 active tssop pw 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pwt active tssop pw 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4075pwte4 active tssop pw 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct4075e active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hct4075ee4 active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered package option addendum www.ti.com 9-aug-2005 addendum-page 1
at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 9-aug-2005 addendum-page 2
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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